View 8XC251TA_46220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Commercial/Express
s Real-time and Programmed Wait State s User-selectable Configurations:
Bus Operation
s Binary-code Compatible with MCS(R) 51 s Pin Compatible with 44-pin PLCC and
40-pin PDIP MCS 51 Sockets
s Register-based MCS(R) 251 Architecture
-- 40-byte Register File -- Registers Accessible as Bytes, Words, or Double Words s Enriched MCS 51 Instruction Set -- 16-bit and 32-bit Arithmetic and Logic Instructions -- Compare and Conditional Jump Instructions -- Expanded Set of Move Instructions s Linear Addressing
s 256-Kbyte Expanded External
-- External Wait States (0-3 wait states) -- Address Range & Memory Mapping -- Page Mode -- Extended Data Float Timings or 8xC251Sx Compatible AC Timings s 32 Programmable I/O Lines
s Eight Maskable Interrupt Sources with
Four Programmable Priority Levels
s Three Flexible 16-bit Timer/counters s Hardware Watchdog Timer s Programmable Counter Array
Code/Data Memory Space
s ROM Options:
16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or without ROM
s 16-bit Internal Code Fetch s 64-Kbyte Extended Stack Space s On-chip Data RAM Options:
-- High-speed Output -- Compare/Capture Operation -- Pulse Width Modulator -- Watchdog Timer s Two Programmable Serial I/O Ports -- Framing Error Detection -- Automatic Address Recognition s High-performance CHMOS Technology
s Static Standby to 24-MHz Operation s Complete System Development
1-Kbyte (TA/TB) or 512-Byte (TP/TQ)
s 8-bit, 2-clock External Code Fetch in
Page Mode
s Fast MCS 251 Instruction Pipeline
Support -- Compatible with Existing Tools -- MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE s Package Options (PDIP and PLCC)
(c) INTEL CORPORATION, 1997
November, 1997
Order Number: 273129-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 8XC251TA/TB/TP/TQ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver CO 80217-9808 or call 1-800-548-4725. Many documents are available for download from Intel's website at http://www.intel.com. Copyright (c) Intel Corporation 1997. *Third party brands and names are the property of their respective owners.
Contents
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS Microcontroller
Commercial/Express
1.0 INTRODUCTION ......................................................................................................................................... 1 2.0 NOMENCLATURE ...................................................................................................................................... 2 3.0 PINOUT ....................................................................................................................................................... 4 4.0 SIGNALS ..................................................................................................................................................... 8 5.0 ADDRESS MAP ........................................................................................................................................ 11 6.0 ELECTRICAL CHARACTERISTICS ......................................................................................................... 12 6.1 D.C. Characteristics ........................................................................................................................... 12 6.2 Definition of AC Symbols ................................................................................................................... 14 6.3 A.C. Characteristics ........................................................................................................................... 14 6.3.1 External Bus Cycles, Nonpage Mode ..................................................................................... 18 6.3.2 External Bus Cycles, Page Mode ........................................................................................... 21 6.3.3 Definition of Real-Time Wait Symbols .................................................................................... 24 6.3.4 External Bus Cycles, Real-Time Wait States .......................................................................... 24 6.4 AC Characteristics -- Serial Port, Shift Register Mode ..................................................................... 28 6.5 External Clock Drive .......................................................................................................................... 29 7.0 THERMAL CHARACTERISTICS .............................................................................................................. 30
ADVANCE INFORMATION
iii
Contents
FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Description of Product Nomenclature ........................................................................................ 2 Proliferation Options .................................................................................................................. 3 Package Information .................................................................................................................. 3 8XC251TA/TB/TP/TQ Pin Assignment ....................................................................................... 6 8XC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category .............. 7 Signal Descriptions .................................................................................................................... 8 Memory Signal Selections (RD1:0) .......................................................................................... 10 8XC251TA/TB/TP/TQ Address Map ......................................................................................... 11 DC Characteristics at VCC = 4.5 - 5.5 V .................................................................................. 12 AC Timing Symbol Definitions ................................................................................................. 14 AC Characteristics ................................................................................................................... 14 Real-time Wait Timing Symbol Definitions ............................................................................... 24 Real-Time Wait AC Timing ...................................................................................................... 27 Serial Port Timing -- Shift Register Mode ............................................................................... 28 External Clock Drive ................................................................................................................ 29 Thermal Characteristics ........................................................................................................... 30 8XC251TA/TB/TP/TQ Block Diagram ........................................................................................ 1 The 8XC251TA/TB/TP/TQ Family Nomenclature....................................................................... 2 8XC251TA/TB/TP/TQ 44-pin PLCC Package ............................................................................ 4 8XC251TA/TB/TP/TQ 40-pin PDIP Packages............................................................................ 5 External Bus Cycle: Code Fetch (Nonpage Mode) .................................................................. 18 External Bus Cycle: Data Read (Nonpage Mode) ................................................................... 19 External Bus Cycle: Data Write (Nonpage Mode).................................................................... 20 External Bus Cycle: Code Fetch (Page Mode) ........................................................................ 21 External Bus Cycle: Data Read (Page Mode).......................................................................... 22 External Bus Cycle: Data Write (Page Mode).......................................................................... 23 External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)................................................ 24 External Bus Cycle: Data Write (Nonpage Mode).................................................................... 25 External Bus Cycle: Code Fetch/Data Read (Page Mode) ...................................................... 26 External Bus Cycle: Data Write (Page Mode).......................................................................... 27 Serial Port Waveform -- Shift Register Mode.......................................................................... 28 External Clock Drive Waveforms ............................................................................................. 29 AC Testing Input, Output Waveforms ...................................................................................... 29 Float Waveforms...................................................................................................................... 30
iv
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
1.0
INTRODUCTION
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251TA/TB/TP/TQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51 microcontrollers. MCS 251 microcontrollers
feature an enriched instruction set, linear addressing, and efficient C-language support. The 8XC251TA/TB/TP/TQ has 512 bytes or 1 Kbyte of on-chip RAM and is available with 8 Kbytes or 16 Kbytes of on-chip ROM, or without ROM. A variety of features can be selected by new user-programmable configurations.
System Bus and I/O Ports P0.7:0 P2.7:0 Code OTPROM/ROM 8 Kbytes or 16 Kbytes
I/O Ports and Peripheral Signals P1.7:0 P3.7:0
Port 0 Drivers
Port 2 Drivers
Data RAM 512 Bytes or 1024 Bytes
Port 1 Drivers
Port 3 Drivers
Memory Data (16)
Memory Address (16)
Watchdog Timer
Bus Interface Code Bus (16) Code Address (24)
Peripheral Interface Timer/ Counters
Instruction Sequencer
Data Address (24)
Interrupt Handler
IB Bus (8)
PCA
SRC2 (8)
Data Bus (8)
SRC1 (8)
ALU
Register File
Data Memory Interface
Clock & Reset
Two Serial I/O Ports
Peripherals
DST (16)
MCS(R) 251 Microcontroller Core
Clock & Reset
8XC251TA/TB/TP/TQ Microcontroller
A4530-01
Figure 1. 8XC251TA/TB/TP/TQ Block Diagram
ADVANCE INFORMATION
1
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
2.0
NOMENCLATURE
X
Te
XX
Pa ck
8
X
o Pr
X
o Pr
XXXXX
o Pr
XX
v De
Figure 2. The 8XC251TA/TB/TP/TQ Family Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Options no mark T Packaging Options N P C Program Memory Options 0 3 Process Information Product Family Device Memory Options C 251 TA TB TP TQ Device Speed 24 Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. Express operating temperature range (-40C to 85C) without Intel standard burn-in. 44-pin Plastic Leaded Chip Carrier (PLCC) 40-pin Plastic Dual In-line Package (PDIP) 40-pin Ceramic Dual In-line Package (Ceramic DIP) Without ROM ROM CHMOS 8-bit control architecture 1-Kbyte RAM/8-Kbyte ROM 1-Kbyte RAM/16-Kbyte ROM or without ROM 512-byte RAM/8-Kbyte ROM 512-byte RAM/16-Kbyte ROM or without ROM External clock frequency
mp
gr
ce
du
ic e
ag ing Op tio ns
am
atu er
ss In f
ct m Fa
e Sp
-m
a re nd
em
or ma tio yO
ed
ily
or
Bu rn -in
n
on pti s
Op tio ns
A2815-01
2
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 2 lists the proliferation options. See Figure 2 for the 8XC251TA/TB/TP/TQ family nomenclature. Table 2. Proliferation Options 8XC251TA/TB/TP/TQ (0 - 24 MHz; 5 V 10%) 80C251TB24 80C251TQ24 83C251TA24 83C251TB24 83C251TP24 83C251TQ24 CPU-only CPU-only ROM ROM ROM ROM
Table lists the 8XC251TA/TB/TP/TQ package definitions. Table 3. Package Information Pkg. N P TN TP Definition 44 ld. PLCC 40 ld. Plastic DIP 44 ld. PLCC 40 ld. Plastic DIP Temperature 0C to +70C 0C to +70C -40C to +85C -40C to +85C
ADVANCE INFORMATION
3
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
3.0
PINOUT
P1.4 / CEX1 P1.3 / CEX0 / TXD1 P1.2 / ECI / RXD1 P1.1 / T2EX P1.0 / T2 VSS1 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3
P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD VCC2 P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
8XC251TA 8XC251TB 8XC251TP 8XC251TQ
View of component as mounted on PC board
18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# VSS2 ALE PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5
P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS VSS2 A8 / P2.0 A9 / P2.1 A10 / P2.2 A11 / P2.3 A12 / P2.4
A4538-01
Figure 3. 8XC251TA/TB/TP/TQ 44-pin PLCC Package
4
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
P1.0 / T2 P1.1 / T2EX P1.2 / ECI / RXD1 P1.3 / CEX0 / TXD1 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28
VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# ALE PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5 A12 / P2.4 A11 / P2.3 A10 / P2.2 A9 / P2.1 A8 / P2.0
8XC251TA 8XC251TB 8XC251TP 8XC251TQ
View of component as mounted on PC board
27 26 25 24 23 22 21
A4532-02
Figure 4. 8XC251TA/TB/TP/TQ 40-pin PDIP Packages
ADVANCE INFORMATION
5
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 4. 8XC251TA/TB/TP/TQ Pin Assignment PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 DIP VSS1 P1.0/T2 P1.1/T2EX P1.2/ECI/RXD1 P1.3/CEX0/TXD1 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK RST P3.0/RXD VCC2 P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD#/A16 XTAL2 XTAL1 VSS Name PLCC 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 DIP VSS2 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 PSEN# ALE VSS2 EA# AD7/P0.7 AD6/P0.6 AD5/P0.5 AD4/P0.4 AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VCC Name
6
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 5. 8XC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category Address & Data Name AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 P3.7/RD#/A16 P1.7/CEX4/A17/WCLK PLCC 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 9 DIP 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 8 VCC VCC2 VSS VSS1 VSS2 Processor Control Name P3.2/INT0# P3.3/INT1# EA# RST XTAL1 XTAL2 PLCC 14 15 35 10 21 20 DIP 12 13 31 9 18 19 Bus Control & Status Name P3.6/WR# P3.7/RD#/A16 ALE PSEN# PLCC 18 19 33 32 DIP 16 17 30 29 EA# Power & Ground Name PLCC 44 12 22 1 23, 34 35 31 20 DIP 40 P1.0/T2 P1.1/T2EX P1.2/ECI/RXD1 P1.3/CEX0/TXD1 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK P3.0/RXD P3.1/TXD P3.4/T0 P3.5/T1 Input/Output Name PLCC 2 3 4 5 6 7 8 9 11 13 16 17 DIP 1 2 3 4 5 6 7 8 10 11 14 15
ADVANCE INFORMATION
7
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
4.0
SIGNALS
Table 6. Signal Descriptions (Sheet 1 of 3)
Signal Name A17
Type O
Description 18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#. Address Line 16. See RD#. Address Lines. Upper address lines for the external bus. Address/Data Lines. Multiplexed lower address lines and data lines for external memory. Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. External Access. Directs program memory accesses to on-chip or offchip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground. PCA External Clock Input. External clock input to the 16-bit PCA timer. External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. Port 0. This is an 8-bit, open-drain, bidirectional I/O port. Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
Alternate Function P1.7/CEX4/ WCLK RD# P2.7:0 P0.7:0
A16 A15:81 AD7:01 ALE
O O I/O O
CEX4:0
I/O
P1.6:4 P1.7/A17/ WAIT# P1.3/TXD1
EA#
I
ECI INT1:0#
I I
P1.2/RXD1 P3.3:2
P0.7:0 P1.0 P1.1 P1.2 P1.7:3
I/O I/O
AD7:0 T2 T2EX ECI/RXD1 CEX3:1 CEX4/A17/ WAIT#/ WCLK CEX0/TXD1 A15:8 RXD TXD INT1:0# T1:0 WR# RD#/A16 --
P2.7:0 P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 PSEN#
I/O I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
O
Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see RD#).
8
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Sheet 2 of 3) Signal Name RD# Type O Description Read or 17th Address Bit (A16). Read signal output to external data memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#). Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC . Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. RXD RXD1 I/O I/O Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. Receive Serial Data 1. RXD1 sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3 for the 2nd serial port. Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. Transmit Serial Data 1. TXD1 outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3 for the 2nd serial port. Supply Voltage. Connect this pin to the +5V supply voltage. Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the +5V supply voltage is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) Circuit Ground. Connect this pin to ground. Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251TA/TB/TP/TQ as a pinfor-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP) Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC251TA/TB/TP/TQ as a pinfor-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) P3.0 P1.2/ECI Alternate Function P3.7/A16
RST
I
--
T1:0 T2
I I/O
P3.5:4 P1.0
T2EX
I
P1.1
TXD TXD1
O O
P3.1 P1.3/CEX0
VCC VCC2
PWR PWR
-- --
VSS VSS1
GND GND
-- --
VSS2
GND
--
ADVANCE INFORMATION
9
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Sheet 3 of 3) Signal Name WAIT# Type I Description Real-time Wait State Input. The real-time WAIT# input is enabled by writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the oscillator frequency. Write. Write signal output to external memory. Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Alternate Function P1.6/CEX3
WCLK
O
P1.7/CEX4/ A17
WR# XTAL1
O I
P3.6 --
XTAL2
O
--
NOTE: The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
Table 7. Memory Signal Selections (RD1:0) RD1:0 00 01 10 P1.7/CEX/ A17/WCLK A17 P1.7/CEX4/ WCLK P1.7/CEX4/ WCLK P1.7/CEX4/ WCLK P3.7/RD#/A16 A16 A16 P3.7 only PSEN# Asserted for all addresses Asserted for all addresses Asserted for all addresses Asserted for 80:0000H WR# Asserted for writes to all memory locations Asserted for writes to all memory locations Asserted for writes to all memory locations Asserted only for writes to MCS 51 microcontroller data memory locations. Features 256-Kbyte external memory 128-Kbyte external memory 64-Kbyte external memory. One additional port pin. 64-Kbyte external memory. Compatible with MCS 51 microcontrollers.
11
RD# asserted for addresses 7F:FFFFH
10
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.0
ADDRESS MAP
Table 8. 8XC251TA/TB/TP/TQ Address Map
Internal Address) FF:FFFFH FF:4000H FF:3FFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH 02:0000H 01:FFFFH 01:0000H 00:FFFFH 00:E000H 00:DFFFH 00:0420H 00:041FH 00:0080H 00:007FH 00:0020H 00:001FH 00:0000H
Description External Memory except the top eight bytes (FF:FFF8H-FF:FFFFH) which are reserved for the configuration array. External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH, 16Kbytes FF:0000H - FF:3FFFH). External Memory Reserved
Notes 1, 3, 10 3, 4, 5 3 6 3 5, 7 7 7 8 2, 9
External Memory External memory or with configuration bit EMAP# = 0, addresses in this range access on-chip code memory in region FF: (16 Kbyte devices only). External Memory On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH) On-chip RAM Storage for R0-R7 of Register File
NOTES: 1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration). 2. The special function registers (SFRs) and the register file have separate internal address spaces. 3. Data in this area is accessible by indirect addressing only. 4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information See EA#. 5. The 16-Kbyte ROM devices allow internal locations FF:2000H-FF:3FFFH to map into region 00:. In this case, if EA# = 1, a data read to 00:E000H-00:FFFFH is redirected to internal ROM (see bit 1 in UCONFIG0). This is not available for 8Kbyte ROM devices. 6. This reserved area returns indeterminate values. 7. Data is accessible by direct and indirect addressing. 8. Data is accessible by direct, indirect, and bit addressing. 9. Data is accessible by direct, indirect, and register addressing. 10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information.
ADVANCE INFORMATION
11
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.0
ELECTRICAL CHARACTERISTICS
NOTICE:This document contains information on products being sampled or in the initial production phase of development. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................. -65C to +150C Voltage: EA# Pin with respect to VSS ............. 0 V to +13.0 V Voltage: Any other Pin with respect to VSS... -0.5 V to +6.5 V IOL per I/O Pin............................................................... 15 mA Power Dissipation ......................................................... 1.5 W
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias): Commercial ................................................. 0C to +70C Express........................................................... -40C to +85C VCC (Digital Supply Voltage) ............................ 4.5 V to 5.5 V VSS ................................................................................... 0 V
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTE:Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.
6.1
D.C. Characteristics
Parameter values apply to all devices unless otherwise indicated. Table 9. DC Characteristics at VCC = 4.5 - 5.5 V (Sheet 1 of 2) Symbol VIL VIL1 VIH VIH1 VOL Parameter Input Low Voltage (except EA#) Input Low Voltage (EA#) Input High Voltage (except XTAL1, RST) Input High Voltage (XTAL1, RST) Output Low Voltage (Port 1, 2, 3) Min -0.5 0 0.2 VCC + 0.9 0.7 VCC Typical Max 0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 VOL1 Output Low Voltage (Port 0, ALE, PSEN#) 0.3 0.45 1.0 VOH Output High Voltage (Port 1, 2, 3, ALE, PSEN#) V CC - 0.3 VCC - 0.7 VCC - 1.5 V V Units V V V V V IOL = 100 A IOL = 1.6 mA IOL = 3.5 mA (Note 1, Note 2) IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA (Note 1, Note 2) IOH = -10 A IOH = -30 A IOH = -60 A (Note 3) Test Conditions
12
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 9. DC Characteristics at VCC = 4.5 - 5.5 V (Sheet 2 of 2) Symbol VOH1 Parameter Output High Voltage (Port 0 in External Address) Output High Voltage (Port 2 in External Address during Page Mode) Logical 0 Input Current (Port 1, 2, 3) Input Leakage Current (Port 0) Logical 1-to-0 Transition Current (Port 1, 2, 3) RST Pulldown Resistor Pin Capacitance Powerdown Current Idle Mode Current Operating Current 40 10 (Note 4) 10 (Note 4) 35 (Note 4) 70 (Note 4) 20 44 83 Min VCC - 0.3 VCC - 0.7 VCC - 1.5 VOH2 VCC - 0.3 VCC - 0.7 VCC - 1.5 -50 +/-10 -650 A A A V Typical Max Units V Test Conditions IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA VIN = 0.45 V 0.45 < VIN < VCC VIN = 2.0 V
IIL ILI ITL
RRST CIO IPD IDL ICC
225
k pF A mA mA FOSC = 24 MHz FOSC = 24 MHz FOSC = 24 MHz TA = 25 C
NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: * Maximum I OL per port pin:10 mA * Maximum I OL per 8-bit port: port 0 26 mA ports 1-3 15 mA * Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the V OH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25C and are not guaranteed.
ADVANCE INFORMATION
13
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.2
Definition of AC Symbols
Table 10. AC Timing Symbol Definitions Signals Conditions H L V X Z High Low Valid No Longer Valid Floating
6.3
A.C. Characteristics
Test Conditions: Capacitive load on all pins = 50 pF. Table 11 lists AC timing parameters for the with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and/or by extending ALE. In the table, Notes 2 and 3 mark parameters affected by an ALE wait state, and Notes 4 and 5 mark parameters affected by a PSEN#/RD#/WR# wait state.
A D L Q R W
Address Data In ALE Data Out RD#/PSEN# WR#
Figure 6 through Figure 8 show the bus cycles with the timing parameters. Table 11. AC Characteristics (Sheet 1 of 4) Symbol FOSC TOSC Parameter XTAL1 Frequency 1/FOSC @ 16MHz @ 24MHz ALE Pulse Width @ 16MHz @ 24MHz Address Valid to ALE Low @ 16MHz @ 24MHz Address Hold after ALE Low @ 16MHz @ 24MHz Address Hold after ALE Low @ 16MHz @ 24MHz RD# or PSEN# Pulse Width @ 16MHz @ 24MHz RD# or PSEN# Pulse Width @ 16MHz @ 24MHz WR# Pulse Width @ 16MHz @ 24MHz WR# Pulse Width @ 16MHz @ 24MHz @ Max FOSC (1) Min N/A N/A Max N/A N/A 62.5 41.7 ns (3) 55.5 34.7 49.5 28.7 10 10 20 20 115 73.4 93 51.4 115 73.4 93 51.4 (0.5+M) 2TOSC -7 ns (3) (0.5+M) 2TOSC-13 ns (4) 10 ns (5) 20 ns (3,4) (1+N) 2TOSC-10 ns (3,5) (1+N) 2TOSC-32 ns (3,4) (1+N) 2TOSC-10 ns (3,5) (1+N) 2TOSC-32 FOSC Variable Min 0 Max 24 Units MHz ns
TLHLL
TAVLL
TLLAX
TLLAXA
TRLRH
TRLRHA
TWLWH
TWLWHA
14
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 2 of 4) Symbol TLLRL Parameter ALE Low to RD# or PSEN# Low @ 16MHz @ 24MHz ALE Low to RD# or PSEN# Low @ 16MHz @ 24MHz ALE High to Address Hold @ 16MHz @ 24MHz ALE High to Address Hold @ 16MHz @ 24MHz RD# or PSEN# Low to Valid Data/Instruction In @ 16MHz @ 24MHz RD# or PSEN# Low to Valid Data/Instruction In @ 16MHz @ 24MHz Data/Instruction Hold after RD# or PSEN# High @ 16MHz @ 24MHz RD#/PSEN# Low to Address Float @ 16MHz @ 24MHz Instruction Float after PSEN# or RD# high @ 16MHz @ 24MHz Instruction Float after PSEN# or RD# high @ 16MHz @ 24MHz Data Float after PSEN# or RD# high @ 16MHz @ 24MHz Data Float after PSEN# or RD# high @ 16MHz @ 24MHz @ Max FOSC (1) Min Max FOSC Variable Min Max Units ns (4) 10 10 10 ns (5) 20 20 98 56.4 77.5 56.7 20 ns (3,4) (1+M) 2TOSC-27 ns (3,5) (0.5+M) 2TOSC +15 ns (3,4) 95 53.4 (1+N) 2TOSC-30 ns (3,5) 75 33.4 (1+N) 2TOSC-50 ns 0 0 0 ns 10 10 10 ns (4) 10 10 10 ns (5) 57.5 36.7 TOSC-5 ns (4) 135 93.4 2TOSC +10 ns (5) 182.5 120.1 3TOSC-5
TLLRLA
TLHAX
TLHAXA
TRLDV
TRLDVA
TRHDX
TRLAZ
TRHDZ1
TRHDZ1A
TRHDZ2
TRHDZ2A
ADVANCE INFORMATION
15
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 3 of 4) Symbol TRHLH2 Parameter RD# or PSEN# High to ALE High (data) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (data) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (Instruction) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (Instruction) @ 16MHz @ 24MHz WR# High to ALE Low @ 16MHz @ 24MHz WR# High to ALE Low @ 16MHz @ 24MHz Address (mux'd) valid to Valid Data/ Instruction In @ 16MHz @ 24MHz Address (mux'd) valid to Valid Data/ Instruction In @ 16MHz @ 24MHz Address (demux'd) valid to Valid Data/Instruction In @ 16MHz @ 24MHz Address (P0)Valid to Valid Instruction In @ 16MHz @ 24MHz Address Valid to RD# or PSEN# Low @ 16MHz @ 24MHz Address Valid to RD# or PSEN# Low @ 16MHz @ 24MHz @ Max FOSC (1) Min Max FOSC Variable Min Max Units ns (4) 135 93.4 2TOSC+10 ns (5) 180.5 118.1 3TOSC -7 ns (4) 10 10 55.5 34.7 10 ns (5) TOSC-7 ns (4) 135 93.4 180.5 118.1 2TOSC+10 ns (5) 3TOSC -7 ns (3,4) 190 106.8 (2+M+N) 2TOSC-60 ns (3,4) 159.5 97.1 (1.5+M+N) 2TOSC-28 ns (3) 212 128.8 (2+M+N) 2TOSC-38 ns (3) 65 23.4 (1+N) 2TOSC-60 ns (3,4) 85 43.4 (1+M) 2TOSC-40 ns (3,5) 72.5 51.7 (0.5+M) 2TOSC+10
TRHLH2A
TRHLH1
TRHLH1A
TWHLH
TWHLHA
TAVDV1
TAVDV1A
TAVDV2
TAVDV3
TAVRL
TAVRLA
16
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 11. AC Characteristics (Sheet 4 of 4) Symbol TAVWL1 Parameter Address (mux'd) Valid to WR# Low @ 16MHz @ 24MHz Address (mux'd) Valid to WR# Low @ 16MHz @ 24MHz Address (demux'd) Valid to WR# Low @ 16MHz @ 24MHz Address (demux'd) Valid to WR# Low @ 16MHz @ 24MHz Data Hold after WR# High @ 16MHz @ 24MHz Data Valid to WR# High @ 16MHz @ 24MHz WR# High to Address Hold @ 16MHz @ 24MHz @ Max FOSC (1) Min Max FOSC Variable Min Max Units ns (3,4) 85 43.4 (1+M) 2TOSC-40 ns (3,5) 72.5 51.7 (0.5+M) 2TOSC +10 ns (3,4) 108 66.4 (1+M) 2TOSC-17 ns (3,5) 135 93.4 49.5 28.7 110 68.4 112 70.4 (1+M) 2TOSC +10 ns TOSC-13 ns (3) (1+N) 2TOSC-15 ns 2TOSC-13
TAVWL1A
TAVWL2
TAVWL2A
TWHQX
TQVWH
TWHAX
NOTES: 1. 24 MHz XTAL Frequency. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for RD#/PSEN#/WR#. 4. Device configured with the default data float timing for fast memory interface (EDF# = 1). 5. Device configured with extended data float timing for slow memory interface (EDF# = 0).
ADVANCE INFORMATION
17
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.1
External Bus Cycles, Nonpage Mode
TOSC XTAL1
ALE
TLHLL TLLRL
TRLRH TRHLH1
RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TLLAX A7:0 TAVRL TAVDV1 TAVDV2 P2/A16/A17 A15:8/A16/A17 TRHDZ1 TRHDX D7:0 Instruction In
The value of this parameter depends on wait states. See the table of AC characteristics.
A4211-03
Figure 5. External Bus Cycle: Code Fetch (Nonpage Mode)
18
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC XTAL1
ALE
TLHLL
TRLRH TLLRL TRHLH2
RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P0 TRHDZ2 TLLAX TRHDX D7:0 Data In
A7:0 TAVRL TAVDV1 TAVDV2
P2/A16/A17
A15:8/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
A4210-03
Figure 6. External Bus Cycle: Data Read (Nonpage Mode)
ADVANCE INFORMATION
19
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC XTAL1
ALE
TLHLL TWLWH TWHLH
WR# TLHAX TAVLL TLLAX P0 A7:0 TAVWL1 TAVWL2 A15:8/A16/A17
TQVWH TWHQX D7:0 Data Out TWHAX
P2/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
A4179-01
Figure 7. External Bus Cycle: Data Write (Nonpage Mode)
20
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.2
External Bus Cycles, Page Mode
TOSC XTAL1
ALE
TLHLL TLLRL
RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P2 TLLAX D7:0 Instruction In TAVDV3 A7:0/A16/A17 Page Hit TRHDZ1 TRHDX D7:0 Instruction In
A15:8 TAVRL TAVDV1 TAVDV2
P0/A16/A17
A7:0/A16/A17 Page Miss
The value of this parameter depends on wait states. See the table of AC characteristics. A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
A4213-02
state (2TOSC); a page miss requires two states (4TOSC).
Figure 8. External Bus Cycle: Code Fetch (Page Mode)
ADVANCE INFORMATION
21
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC XTAL1
ALE
TLHLL TLLRL
TRLRH TRHLH2
RD#/PSEN# TRLDV TRLAZ TLHAX TAVLL P2 TRHDZ2 TLLAX TRHDX D7:0 Data In
A15:8 TAVRL TAVDV1 TAVDV2
P0/A16/A17
A7:0/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
A4212-03
Figure 9. External Bus Cycle: Data Read (Page Mode)
22
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
TOSC XTAL1
ALE
TLHLL TWLWH TWHLH
WR# TLHAX TAVLL TLLAX P2 A15:8 TAVWL1 TAVWL2 A7:0/A16/A17
TQVWH TWHQX D7:0 Data Out TWHAX
P0/A16/A17
The value of this parameter depends on wait states. See the table of AC characteristics.
A4182-01
Figure 10. External Bus Cycle: Data Write (Page Mode)
ADVANCE INFORMATION
23
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.3.3
Definition of Real-Time Wait Symbols Table 12. Real-time Wait Timing Symbol Definitions Signals A D C Y W R Address Data WCLK WAIT# WR# RD#/PSEN# L X V Conditions Low Hold Setup
6.3.4
External Bus Cycles, Real-Time Wait States
State 1 WCLK
State 2
State 3
State 1 (next cycle)
ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P0 P2
TCLYX min TCLYX max RD#/PSEN# stretched
A7:0 A15:8
D7:0
stretched stretched
A7:0 A15:8
A5000-02
Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)
24
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1 WCLK
State 2
State 3
State 4
TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P0 P2 WR# stretched TCLYX max
A7:0 A15:8
D7:0
stretched stretched
A5002-02
Figure 12. External Bus Cycle: Data Write (Nonpage Mode)
ADVANCE INFORMATION
25
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1 WCLK
State 2
State 3
State 1 (next cycle)
ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P2 P0
TCLYX min TCLYX max RD#/PSEN# stretched
A15:8 A7:0
D7:0
stretched stretched
A15:8 A7:0
A5001-02
Figure 13. External Bus Cycle: Code Fetch/Data Read (Page Mode)
26
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
State 1 WCLK
State 2
State 3
State 4
TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P2 P0 WR# stretched TCLYX max
A15:8 A7:0
D7:0
stretched stretched
A5003-02
Figure 14. External Bus Cycle: Data Write (Page Mode)
Table 13. Real-Time Wait AC Timing Symbol TCLYV TCLYX TRLYV TRLYVA TRLYX TWLYV TWLYVA TWLYX Parameter Wait Clock Low to Wait Set-up Wait Hold after Wait Clock Low PSEN#/RD# Low to Wait Set-up PSEN#/RD# Low to Wait Set-up Wait Hold after PSEN#/RD# Low WR# Low to Wait Set-up WR# Low to Wait Set-up Wait Hold after WR# Low Min 0 (2W)TOSC + 5 0 0 (2W)TOSC + 5 0 0 (2W)TOSC + 5 Max TOSC - 13 (1+2W)TOSC - 20 TOSC - 13 TOSC - 35 (1+2W)TOSC - 20 TOSC - 13 TOSC - 35 (1+2W)TOSC - 20 Units ns ns (1) ns ns (2) ns (1) ns ns (2) ns (1)
NOTES: 1. W = 0, 1, 2 -- is the number of real time wait states. 2. Device configured with the extended data float timing.
ADVANCE INFORMATION
27
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.4
AC Characteristics -- Serial Port, Shift Register Mode
Table 14. Serial Port Timing -- Shift Register Mode
Symbol TXLXL TQVSH TXHQX TXHDX TXHDV
Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid
Min 12TOSC 10TOSC - 133 2TOSC - 117 0
Max
Units ns ns ns ns
10TOSC - 133
ns
TXLXL
TXD
TXHQX TQVXH
Set TI
2 3 4 5 6 7
RXD (Out)
0
1
TXHDV
TAV
TXHDX Valid Valid Valid Valid Valid Valid
Set RI
Valid
RXD (In)
Valid
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 15. Serial Port Waveform -- Shift Register Mode
28
ADVANCE INFORMATION
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
6.5
External Clock Drive
Table 15. External Clock Drive Symbol 1/TCLCL TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency (FOSC) High Time Low Time Rise Time Fall Time 20 20 10 10 Min Max 24 Units MHz ns ns ns ns
TCLCH
VCC - 0.5 0.7 VCC
TCHCX
TCLCX 0.45 V
0.2 VCC - 0.1
TCHCL
TCLCL
A4119-01
Figure 16. External Clock Drive Waveforms
Inputs VCC - 0.5
0.45 V
Outputs 0.2 VCC + 0.9 0.2 VCC - 0.1 VIH MIN VOL MAX
AC inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 17. AC Testing Input, Output Waveforms
ADVANCE INFORMATION
29
8XC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.
A4117-01
Figure 18. Float Waveforms
7.0
THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. Table 16. Thermal Characteristics Package Type 44-pin PLCC 40-pin PDIP JA 46C/W 45C/W JC 16C/W 16C/W
30
ADVANCE INFORMATION

▲Up To Search▲

Price & Availability of 8XC251TA

	To Download 8XC251TA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .